View R7731A_4834816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

R7731A 1 R7731A-10 august 2011 www.richtek.com general description the R7731A is a high-performance, low cost, low start-up current and current mode pwm controller with burst triple mode to support green mode power saving operation. the R7731A integrates functions of soft start, under voltage lockout (uvlo), leading edge blanking (leb), over temperature protection (otp) and internal slope compensation. it provides the users a superior ac/dc power application of higher efficiency, low external component counts and lower cost solution. to protect the external power mosfet from being damaged by supply over voltage, the R7731A output driver is clamped at 12v. furthermore, R7731A features fruitful protections like over load protection (olp) and over voltage protection (ovp) to eliminate the external protection circuits and provide reliable operation. R7731A is available in sot-23-6 and dip-8 packages. burst triple mode pwm flyback controller features z z z z z very low start-up current (<30 a) z z z z z 10/14v uvlo z z z z z soft start function z z z z z current mode control z z z z z jittering switching frequency z z z z z internal leading edge blanking z z z z z built-in slope compensation z z z z z burst triple mode pwm for green-mode z z z z z cycle-by-cycle current limit z z z z z feedback open protection z z z z z over voltage protection z z z z z over temperature protection z z z z z over load protection z z z z z soft driving for reducing emi z z z z z driver capability 200ma z z z z z high noise immunity z z z z z opto-coupler short protection z z z z z rohs compliant and halogen free applications z adaptor and battery charger z atx standby power z set-top box (stb) z dvd and cd(r) z tv/monitor standby power z pc peripherals ordering information R7731A package type e : sot-23-6 n : dip-8 lead plating system g : green (halogen free and pb free) note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information idp=w idp= : product code w : date code R7731Agn : product number ymdnn : date code R7731Age R7731Age richtek R7731A gnymdnn
R7731A 2 R7731A-10 august 2011 www.richtek.com pin no. sot-23-6 dip8 pin name pin function 1 8 gnd ground. 2 7 comp comparator input. by connecting an opto-coupler to this pin, the peak current set point is adjusted accordingly to the output power requirement. 3 5 rt set the switching frequency by connecting a resistor to gnd. 4 4 cs primary current sense. 5 2 vdd ic power supply. 6 1 gate gate driver output to drive the external mosfet. -- 3, 6 nc no internal connection. functional pin description pin configurations (top view) sot-23-6 dip-8 typical application circuit gnd comp rt gate vdd cs 4 23 5 6 6 7 8 4 5 23 gate vdd nc cs rt nc comp gnd vo+ rt comp gnd vdd gate cs R7731A ac mains (90v to 265v) vo- * * : see application information
R7731A 3 R7731A-10 august 2011 www.richtek.com function block diagram leb vdd r s q otp ss x3 slope ramp burst triple mode comp v burl v burh v dd pwm comparator counter shutdown logic comp open sensing brown out sensing dmax jittering oscillator por 27v bias & bandgap uvlo ovp rt gate gnd cs comp 14v/10v olp constant power soft driver + - + - + - -
R7731A 4 R7731A-10 august 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit vdd section v dd over voltage protection level v ovp 25.5 27 28.5 v on threshold voltage v th_on 13 14 15 v v dd on/off hysteresis v dd_hys 3 4 5 v start-up current i dd_st v dd = v th_on ? 0.1v -- 20 30 a operating current i dd_op v dd = 15v, r t = 100k , gate = open, v comp = 2.5v -- 1.1 2.2 ma vdd holdup mode hysteresis ending level v dd_hys v comp < 1.6v -- 11.5 -- v vdd holdup mode entry level v dd_low v comp < 1.6v -- 11 -- v v dd clamp voltage v dd_clamp -- 29 -- v oscillator section (rt pin) normal pwm frequency f osc r t = 100k 60 65 70 khz to be continued recommended operating conditions (note 4) z supply input voltage, v dd ------------------------------------------------------------------------------------------------- 12v to 25v z operating frequency ------------------------------------------------------------------------------------------------------- 50k to 130khz z junction temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v dd ------------------------------------------------------------------------------------------------- ? 0.3v to 30v z gate pin ---------------------------------------------------------------------------------------------------------------------- ? 0.3v to 20v z rt, comp, cs pin ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z i dd ------------------------------------------------------------------------------------------------------------------------------- 10ma z power dissipation, p d @ t a = 25 c sot-23-6 ---------------------------------------------------------------------------------------------------------------------- 0.4w dip-8 --------------------------------------------------------------------------------------------------------------------------- 0.714w z package thermal resistance (note 2) sot-23-6, ja ----------------------------------------------------------------------------------------------------------------- 250 c/w dip-8, ja ---------------------------------------------------------------------------------------------------------------------- 140 c/w z junction temperature ------------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------------ 4kv mm (ma chine mode) -------------------------------------------------------------------------------------------------------- 250v (v dd = 15v, vdd bypass capacitor=0.1 f, r t = 100k , t a = 25 c, unless otherwise specified)
R7731A 5 R7731A-10 august 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective single layer thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. parameter symbol test conditions min typ max unit frequency jittering range -- 6 -- % pwm frequency jitter period t jit for 65 khz -- 4 -- ms maximum duty cycle d max 70 75 80 % frequency variation versus v dd deviation f dv v dd = 12v to 25v -- -- 2 % frequency variation versus temperature deviation f dt t a = ? 30 c to 105 c (note 5) -- -- 5 % comp input section open loop voltage v comp_op comp pin open 5.2 5.6 6 v comp open-loop protection delay cycles t olp r t = 100k -- 60 -- ms short circuit current i zero v comp = 0v -- 1.2 2.2 ma current-sense section initial peak current limit offset v csth 0.8 0.85 0.9 v leading edge blanking time t leb -- 420 520 ns propagation delay time t pd -- 100 -- ns gate section rising time t r v dd = 15v, c l = 1nf -- 250 350 ns falling time t f v dd = 15v, c l = 1nf -- 150 250 ns gate output clamping voltage v clamp v dd = 22v -- 12 -- v over temperature protection t otp 140 -- -- c otp hysteresis t otp_hys -- 30 -- c
R7731A 6 R7731A-10 august 2011 www.richtek.com d max vs. temperature 70 71 72 73 74 75 76 77 78 79 80 -40-20 0 20406080100120 temperature (c) d max (%) typical operating characteristics v th vs. temperature 9 10 11 12 13 14 15 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) v dd (v) v th_on v th_off i dd_st vs. temperature 10 12 14 16 18 20 22 24 26 28 -40 -15 10 35 60 85 110 135 temperature (c) i dd_st (a) v dd = 13v i dd_op vs. temperature 1.25 1.30 1.35 1.40 1.45 1.50 1.55 -40 -15 10 35 60 85 110 135 temperature (c) i dd_op (ma) v comp = 2v, c l = 1nf v dd = 11v v dd = 27v v dd = 15v f osc vs. temperature 57 58 59 60 61 62 63 -40 -15 10 35 60 85 110 135 temperature (c) f osc (khz) v dd = 11v v dd = 27v v dd = 15v v comp vs. temperature 5.40 5.44 5.48 5.52 5.56 5.60 -40 -20 0 20 40 60 80 100 120 temperature (c) v comp comp open voltage
R7731A 7 R7731A-10 august 2011 www.richtek.com v clamp vs. v dd 7 8 9 10 11 12 13 11 12 13 14 15 16 17 18 19 20 21 22 v dd (v) v clamp (v) i source = 20ma v gate_off vs. v dd 400 425 450 475 500 525 550 575 600 11 12 13 14 15 16 17 18 19 20 21 22 v dd (v) v gate_off (mv) i sink = 20ma i supply vs. temperature 0.30 0.35 0.40 0.45 0.50 -40 -20 0 20 40 60 80 100 120 temperature (c) i supply (ma) comp pin open no gate output i supply = i dd_op ? i comp i supply vs. v dd 0.408 0.410 0.412 0.414 0.416 0.418 0.420 0.422 0.424 0.426 11 12 13 14 15 16 17 18 19 20 21 22 v dd (v) i supply (ma) comp pin open no gate output i supply = i dd_op ? i comp v clamp vs. temperature 10.0 10.5 11.0 11.5 12.0 12.5 13.0 -40 -15 10 35 60 85 110 135 temperature (c) v clamp (v) v dd = 20v, c l = 1nf gate vs. temperature 0 50 100 150 200 250 300 350 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) gate (ns) v dd = 20v, c l = 1nf rising falling
R7731A 8 R7731A-10 august 2011 www.richtek.com v csth vs. temperature 0.800 0.815 0.830 0.845 0.860 0.875 0.890 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) v csth (v)
R7731A 9 R7731A-10 august 2011 www.richtek.com application information uvlo under voltage lockout (uvlo) block is to ensure v dd has reached proper operation voltage before we enable the whole ic blocks. to provide better temperature coefficient and precise uvlo threshold voltage, the reference voltage of hysteresis voltage (10v / 14v) is from band-gap block directly. by this way, R7731A can operate more reliable in different environments. the maximum start-up current (30 a) is only for leakage current of ic at uvlo(on)-0.1v. the external al-capacitor on vdd may have 5 to 6 a extra leakage current. so designed start-up current of the system should exceed 36 a or more and ic can start up normally. in addition, designed start-up current of system should be less than 380 a, and ic can work normally at hiccup mode. jittering oscillator for better emi performance, R7731A will operate the system with 6% frequency deviation around setting frequency. to guarantee precise frequency, it is trimmed to 5% tolerance. it also generates slope compensation saw-tooth, 75% maximum duty cycle pulse and overload protection slope. by adjusting resistor of rt pin according to the following formula : figure 1. competitor v cs v out v cs (500mv/div) v out (2v/div) ) (k r 6500 (khz) f t osc = it can typically operate between 50khz to 130khz. note that rt pin can ' t be short or open otherwise oscillator will not operate. built-in slope compensation to reduce component counts, slope compensation is implemented by internal built-in saw-tooth. since it ' s built- in, it ' s compromised between loop gain and sub-harmonic reduction. in general design, it can cancel sub-harmonic to 90vac. leading edge blanking (leb) mosfet c oss , secondary rectifier reverse recovery current and gate driver sourcing current comprise initial current spike. the spike will seriously disturb current mode operation especially at light load and high line. R7731A provides built-in 420ns leb to guarantee proper operation in diverse design. noise immunity current mode controller is very sensitive to noise. R7731A takes the advantages of richtek long term experience in designing high noise immunity current mode circuit and layout. also, we amplify current sense signal to compare with feedback signal instead of dividing feedback signal. all the effort is to provide clean and reliable current mode operation. soft-start during initial power on, especially at high line, current spike is kind of unlimited by current limit. therefore, besides cycle-by-cycle current limiting, R7731A still provides soft-start function. it effectively suppresses the start-up current spike. as shown in the figure 1 and figure 2, the start-up v cs is about 0.3v lower than competitor. the typical soft-start duration is 4ms (r t = 100k ). again, this will provide more reliable operation and possibility to use smaller current rating power mosfet.
R7731A 10 R7731A-10 august 2011 www.richtek.com gate driver a totem pole gate driver is fine tuned to meet both emi and efficiency requirement in low power application. an internal pull low circuit is activated after pretty low v dd to prevent external mosfet from accidentally turning on during uvlo. burst triple mode to fulfill green mode requirement, there are 3 operation modes in R7731A. please also refer to figure 3 for details. ` ` ` ` ` pwm mode for most of load condition, the circuit will run at traditional pwm current mode. ` ` ` ` ` burst mode during light load, switching loss will dominate the power efficien cy calculation. this mode is to cut switching loss. as shown in figure 3, when the output load gets light, feedback signal drops and touches v burl (typical value is 1.75v). clock signal will be blanked and system ceases to switching. after v out drops and feedback signal goes back to v burh (1.8v, typically), switching will be resumed. burst mode so far is widely used in low power application because it ' s simple, reliable and will not have any patent infringement issue. ` ` ` ` ` vdd holdup mode when the v dd drops down to v dd turn off threshold voltage, the system will be shut down. during shut down period, controller does nothing to any load change and might cause v out down. to avoid this, when v dd drops to a setting threshold, 11v, the hysteresis comparator will bypass pwm and burst mode loop and force switching at a very lo w level to supply energy to vdd pin. the designed value is 11.25v with 0.5v hysteresis band. furthermore, vdd holdup mode is only designed to prevent v dd from touching turn off threshold voltage under light load or load transient moment. relative to burst mode, switching loss will increase on the system at vdd holdup mode, so it is highly recommended that the system should avoid operating at this mode during light load or no load condition, normally. figure 3. burst triple mode figure 2. R7731A v cs v out v cs (500mv/div) v out (2v/div) load v dd light load normal operation no load v comp v gate v burh v burl (vdd holdup mode) v dd_high v dd_low
R7731A 11 R7731A-10 august 2011 www.richtek.com protection R7731A provides fruitful protection functions that intend to protect system from being damaged. all the protection functions can be listed as below : ` ` ` ` ` cycle-by-cycle current limit this is a basic but very useful function and it can be implemented easily in current mode controller. ` ` ` ` ` over load protection long time cycle-by-cycle current limit will lead to system thermal stress. to further protect system, system will be shut down after about 4096 clock cycles. it ' s about 60ms delay in 67khz operation. after shutdown, system will resume and behave as hiccup. by proper start-up resistor design, thermal will be averaged to an acceptable level over the on/off cycle of ic. this will last until fault is removed. # it's highly recommended to add a resistor in parallel with the opto-coupler. to provide sufficient bias current to make tl-431 regulate properly, 1.2k resistor is suggested. ` ` ` ` ` brownout protection during heavy load, this will trigger 60ms protection and shut down the system. if it ' s in light load condition, system will be shut down after v dd is running low and triggers uvlo. ` ` ` ` ` ovp output voltage can be roughly sensed by vdd pin.if the sensed voltage reaches 27v threshold, system will be shut down after 20 s deglitch delay. ` ` ` ` ` feedback open and opto-coupler short this will trigger ovp or 60ms delay protection. it depends on which one occurs first. ` ` ` ` ` otp internal otp function will protect the controller itself from suffering thermal stress and permanent damage. it stops the system from switching until the temperature is under threshold level. meanwhile, if v dd reaches v dd turn off threshold voltage, system will hiccup till over temperature condition is gone. figure 4. r-c filter on cs pin negative voltage spike on each pin negative voltage (< ? 0.3v) on each pin will cause substrate injection. it leads to controller damage or circuit false trigger. generally, it happens at cs pin due to negative spike because of improper layout or inductive current sense resistor. therefore, it is highly recommended to add a r-c filter to avoid cs pin damage, as shown in figure 4. proper layout and careful circuit design should be done to guarantee yield rate in mass production. vdd gate cs R7731A ac mains (90v to 265v) r-c filter
R7731A 12 R7731A-10 august 2011 www.richtek.com auxiliary ground (c) ic ground (d) trace trace trace mosfet ground (b) c bulk ground (a) rt comp gnd gate cs R7731A ac mains (90v to 265v) vdd c bulk (a) (d) (b) (1) (c) (2) + figure 5. pcb layout guide layout consideration a proper pcb layout can abate unknown noise interference and emi issue in the switching power supply. please refer to the guidelines when you want to design pcb layout for switching power supply: the current path (1) from bulk capacitor, transformer, mosfet, rcs return to bulk capacitor is a huge high frequency current loop. it must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as ic control circuit paths, especially. besides, the path (2) from rcd snubber circuit to mosfet is also a high switching loop, too. so keep it as small as possible. it is good for reducing noise, output ripple and emi issue to separate ground traces of bulk capacitor (a), mosfet (b), auxiliary winding (c) and ic control circuit (d). finally, connect them together on bulk capacitor ground (a). the areas of these ground traces should be kept large. placing bypass capacitor for abating noise on ic is highly recommended. the bypass capacitor should be placed as close to controller as possible. to minimize reflected trace inductance and emi minimize the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor. in addition, provide sufficient copper area at the anode and cathode terminal of the diode for heatsinking. provide a larger area at the quiet cathode terminal. a large anode area can increase high-frequency radiated emi.
R7731A 13 R7731A-10 august 2011 www.richtek.com outline dimension a a1 e b b d c h l sot-23-6 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.031 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024
R7731A 14 R7731A-10 august 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com j a b e c i d l f 8-lead dip plastic package dimensions in millimeters dimensions in inches symbol min max min max a 9.068 9.627 0.357 0.379 b 6.198 6.604 0.244 0.260 c 3.556 4.318 0.140 0.170 d 0.356 0.559 0.014 0.022 e 1.397 1.651 0.055 0.065 f 2.337 2.743 0.092 0.108 i 3.048 3.556 0.120 0.140 j 7.366 8.255 0.290 0.325 l 0.381 0.015

▲Up To Search▲

Price & Availability of R7731A

	To Download R7731A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .